4：1 MUX电路设计毕业论文

论文总字数：24499字

摘 要

数据复接器是数字通信通道中的关键模块，国内外对高速复接电路的研究始终在推进。近些年随着工艺不断发展，基于CMOS工艺可以实现多种高速应用，其中MOS电流模式逻辑（MCML）是应用在高速、低功耗和混合信号领域新颖有用的逻辑风格，部分应用可达Gbps。

本论文深入分析电路原理，提出了一种基于CMOS晶体管高速工作的反馈MOS电流模式逻辑的数据复接器。该4:1数据复接器基于树型结构设计，使用2:1MUX作为基本单元分级组合构成较大输入通道数的复接器。在半速树类型中，时钟频率是串行数据速度的一半，因此提高数据码率。本论文的高速2:1MUX由5个D锁存器和1个选择器构成。锁存器和选择器都采用MCML逻辑风格，使用偏置电路引入静态电流源I_CS，使用有源负载PMOS做上拉电阻。此外，本论文设计了时钟缓冲电路和单转双电路，将时钟和数据转化为差分信号输入系统。综合各模块，本文完成了4:1MUX晶体管级电路设计。

本复接器电路基于0.5um CSMC CMOS工艺，电路使用Cadence进行绘制和仿真。电源电压为3.3V，电流源静态电流80uA的条件下，输出摆幅为0.8V。输入4路62.5M数据信号，输出1路250M数据信号，数据正确，失真度小。综合芯片设计的性能和功耗平衡，所设计的MUX基本满足课题数据复接要求，功耗为50mW。

关键词： MOS电流模逻辑，MCML，高速，数据复接，低功耗

Abstract

Multiplexer is the key module in the digital communication system, and the research on the high speed multiplexing circuit is always on progressing both at home and abroad. Recently, with the continuous development of technology, a variety of high-speed applications could be achieved based on the CMOS technology. As a kind of novel and useful logic style, the MOS Current Mode Logic (MCML) is used in high-speed, low power and mixed signal field. The speed of some applications are up to Gbps. In this paper, I try to realize a 4:1 multiplexer with MCML logic based on in-depth analysis of circuit theory.

A multiplexer based on feedback MOS current mode logic (MCML) is proposed for the high-speed operation of CMOS transistors. The design of 4:1MUX is based on the tree structure, combining of 2:1MUX as the basic unit, in order to constitute of the large input channels number of multiplexer. In the half-speed tree type, the clock frequency is half the serial data speed, thus increasing the data bit rate. High speed 2:1MUX consists of 5 D-latches and 1 Selector. Both the latch and the selector use the MCML logic style, in which introducing the quiescent current using the bias current I_CS, and using the active load PMOS as the pull-up resistor. In addition, I design the clock buffer circuit and single-turn dual circuit, in order to turn the clock and data siginal into differential input signal.Based on the modules, this paper completes the 4: 1 MUX transistor-level circuit design.

The multiplexer circuit is based on 0.5um CSMC CMOS technology and the circuit is plotted and simulated with Cadence. Under the conditions that power supply voltage is 3.3V, current source quiescent current is 80uA, the output swing is 0.8V. With the input 4-way 62.5M data signal, the output is 250M data signal, and the data is correct with small distortion. Balancing the performance and power, the design of the MUX can meet the basic requirements of the requirements of data multiplexing, and the power consumption of 50mW.

KEY WORDS: MOS current mode logic, MCML, high speed, multiplexing, low power dissipation

目 录

摘 要 I

Abstract II

目 录 III

第一章 绪论 5

1.1 研究背景 5

1.2 国内外研究现状 5

1.3 论文研究内容及意义 6

1.4 论文组织结构 7

第二章 4:1MUX设计原理 8

2.1 数据复接原理 8

2.1.1 复接技术简介 8

2.1.2 时分复用 8

2.2 复接器的基本结构 9

2.2.1 串行复接器 9

2.2.2 并行复接器 10

2.2.3 树型复接器 11

2.3 MCML逻辑基本原理 13

2.4 本章小结 14

第三章 4:1MUX系统设计 15

3.1 4:1MUX设计说明 15

3.1.1 复接器系统概述 15

3.1.2 复接器系统结构 15

3.2 总体电路结构图 15

3.3 MCML逻辑设计要点 16

3.3.1 MCML的优缺点 16

3.3.2 MCML设计要点 17

3.4 本章小结 17

第四章 4:1MUX基本单元设计 19

4.1 基于MCML单元电路设计 19

4.1.1 反相器 19

4.1.2 一般逻辑门 21

4.1.3 D锁存器 23

4.2 MUX单元电路性能分析 24

4.2.1 电压传输特性 24

4.2.2 扇入/扇出能力 25

4.2.3 传输延迟效应 26

4.3 本章小结 27

第五章 4:1MUX模块总体电路设计与仿真 28

5.1 2:1MUX设计 28

5.2 时钟分频器 29

5.3 时钟输入缓冲电路 29

5.4 数据单转双电路 30

5.5 综合电路仿真 30

5.6 本章小结 31

第六章 总结与展望 32

6.1 总结 32

6.2 展望 32

参考文献 34

致谢 35

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